Biography
Dr Zhenyu Cai is an EPSRC Quantum Technologies Fellow and Principal Investigator in Engineering Science at the University of Oxford. His research focuses on quantum error correction, error mitigation, and their hardware-adapted implementation for different applications, aiming to enable resource-efficient, noise-robust pathways to scalable quantum computing.
He previously held a Junior Research Fellowship at St John’s College (2020–2024) and completed his undergraduate studies in Cambridge and DPhil in Oxford.
In addition to leading a £2.2 million EPSRC Fellowship ( £ 1.7 million funding with £500k industrial support), he is an investigator on several other grants totalling over £1.3 million. He maintains active collaboration with industrial partners and is the lead inventor on four patents.
Dr Cai serves on the organising committee of the £3 million RoaRQ Programme and the SEEQA conference, contributing to UK-wide efforts in building robust, scalable quantum technologies.
Most Recent Publications
Quantum information processing, sensing, and communications: their myths, realities, and futures
Quantum information processing, sensing, and communications: their myths, realities, and futures
Pipeline quantum processor architecture for silicon spin qubits
Pipeline quantum processor architecture for silicon spin qubits
Quantum error mitigated classical shadows
Quantum error mitigated classical shadows
Quantum error mitigation
Quantum error mitigation
Looped pipelines enabling effective 3D qubit lattices in a strictly 2D device
Looped pipelines enabling effective 3D qubit lattices in a strictly 2D device
Research Interest
- Quantum Error Correction
- Quantum Error Mitigation
- Hardware Implementation and Architectures for Quantum Algorithms
Most Recent Publications
Quantum information processing, sensing, and communications: their myths, realities, and futures
Quantum information processing, sensing, and communications: their myths, realities, and futures
Pipeline quantum processor architecture for silicon spin qubits
Pipeline quantum processor architecture for silicon spin qubits
Quantum error mitigated classical shadows
Quantum error mitigated classical shadows
Quantum error mitigation
Quantum error mitigation
Looped pipelines enabling effective 3D qubit lattices in a strictly 2D device
Looped pipelines enabling effective 3D qubit lattices in a strictly 2D device
